The NSF has funded projects that will investigate how deep learning algorithms run on FPGAs and across systems using the high-performance RDMA interconnect. Another project, led by Andrew Ng and ...

For both gray-scale and color image applications in an FPGA, we have implemented block truncation coding (BTC), a lossy image-compression algorithm with proven value in applications that don't require ...

Field-programmable gate arrays (FPGAs) offer a unique platform for the implementation of high-performance sorting algorithms by combining inherent parallelism with customisable hardware architectures.

Using a design flow put together by Mentor Graphics and Altera, designers can implement complex DSP algorithms in high-performance FPGAs directly from ANSI C++ code. The flow, which is based on ...

The PROC reconfigurable systems are used to accelerate complex algorithms that include DSP, image processing, national security and other performance critical domains.

CoDeveloper for Virtex-4 allows software programmers and FPGA designers to describe parallel algorithms for image processing, DSP, encryption and other processing-intensive applications using standard ...

The real beauty of this algorithm is that you can implement it with a very small FPGA footprint. CORDIC requires only a small lookup table, along with logic to perform shifts and additions.

Microchip has released a C++ algorithm high-level synthesis design workflow for its PolarFire FPGAs. “A large majority of edge compute, computer vision and industrial control algorithms are developed ...

Today Intel announced record results on a new benchmark in deep learning and convolutional neural networks (CNN). ZTE’s engineers used Intel’s midrange Arria 10 FPGA for a cloud inferencing ...