GitHub

This repository contains four laboratory assignments covering combinational circuits, sequential logic with Verilog, FPGA implementation, and memory systems.

Simplify and implement a circuit with inputs A1, A0, B1, B0 and outputs X, Y, Z using only 74LS ICs in Logisim. Learn Boolean algebra simplification and basic gate usage. Lab 2: Multiplexers, Decoders ...
GitHub

sanjeev-vlsi-design/Sequential-Multiplier-4Bit

4-Bit Sequential Multiplier Overview This project implements a 4-bit Sequential Multiplier, designed to multiply two 4-bit binary numbers using sequential logic. The design leverages a step-by-step ...
mccormick.northwestern.edu

COMP_ENG 303: Advanced Digital Design

Overview of digital logic design. Implementation technologies, timing in combinational and sequential circuits, EDA tools, basic arithmetic units, introduction to simulation and synthesis using ...
IEEE

Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients

Abstract: As CMOS device sizes continue to scale down, radiation-related reliability issues are of ever-growing concern. Single event double node upsets (SEDUs) in sequential logic and single event ...
IEEE

An applying aspect-oriented concept to sequential logic design

Abstract: Because of rapid hardware design's evolution, hardware circuits are more complex. Hardware designer would not spend too much time to produce the circuits. One of hardware designers' problems ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...