4-bit-Multiplier-using-Modified-Booth-Algorithm The idea of this design is to implement the modified Booth algorithm to create 4 bit SFQ multiplier. In more detail, we have designed a 4-bit multiplier ...

In this paper, a new architecture of hybrid Modified Booth Encoded Algorithm (MBE) and Carry Save Adder (CSA) is developed as fast multiplier architecture. Altera Quartus II platform is used to run ...

This paper presents an adiabatic array multiplier based on modified Booth algorithm. It is composed of Booth encoders, a multiplier array containing partial product generators and 1-bit (half and full ...