GitHub

2-Bit Comparator Using Logic Gates

This is a simple project where I built and simulated a 2-bit digital comparator using only basic logic gates in Logisim Evolution. Instead of using the built-in comparator blocks, I created the logic ...
IEEE

FinFET-Premised 1-Bit Comparator Design Using CPTL and DCVSPG Techniques

Abstract: For the efficient design of digital circuits many digital designing techniques have been characterized by Pass Transistor Logic family. Pass transistor-based techniques prefer N-channel ...
EDN

Using auto-zero comparator techniques to improve PWM performance (Part 1 of 2)

Comparators are subject to input offset errors that can be either systematic or layout related. Two applications of comparators in a PWM controller are detecting when there is no current in the ...
EDN

Using auto-zero comparator techniques to improve PWM performance (Part 2 of 2)

Another application of auto-zeroing comparators is in the main control loop of a PWM system. The comparator in this application looks at the difference between a ...
IEEE

Design of Low Power and High Speed 4-Bit Comparator Using Transmission Gate

Abstract: This paper present two different designs for 4-bit comparator, one is using CMOS technology and another is designed using Transmission Gate. Firstly we have designed various CMOS devices and ...
TechRepublic

Design and Implementation of 16-Bit Magnitude Comparator Using Efficient Low Power High Performance Full Adders

In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The paper attempts to examine the features of certain adder ...