IEEE

Modified Binary Multiplier Circuit Based on Vedic Mathematics

Abstract: This paper presents a modified binary multiplier using Vedic mathematics. The paper proposes a modification in the previously published Vedic multiplier circuit. The suggested modified Vedic ...
IEEE

Design of a novel reversible multiplier circuit using modified full adder

Abstract: Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics, ...
Ars Technica

VHDL 4 bit multiplier

I am new to VHDL programming (although I've programmed in other languages like C++, java, etc.). I've been searching the web for help in writing a 4 bit multiplier (i.e. 0111 x 0110). I found sample ...
TechRepublic

Design of High Speed Hardware Efficient 4-Bit SFQ Multiplier

A 2-bit booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The booth encoding method is one of the algorithms to obtain partial products. With ...