TechRepublic

Design of High Speed Hardware Efficient 4-Bit SFQ Multiplier

A 2-bit booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The booth encoding method is one of the algorithms to obtain partial products. With ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...