GitHub

RFSoC-4x2-FPGA-implementation-of-Product-Codes

In this repository, the implementation of an eBCH(256,239,2) product code encoder and a decoder on an RFSoC4x2 FPGA board is presented. The implementation is optimized to get a low BER rate of 10-14, ...
GitHub

4-2-encoder-using-verilog-Xillinx

A 4:2 priority encoder designed in Verilog and tested using Xilinx ISE. Converts 4 input lines into a 2-bit binary output representing the highest-priority active input. Includes testbench and ...
IEEE

Implementation of Low-Density Parity-Check (LDPC) Codes in Verilog HDL

Abstract: This work presents FPGA implementation of Low-Density Parity-Check (LDPC) encoder. Low-density coding is an effective method for ensuring reliable ...
IEEE

Verilog HDL model based thermometer-to-binary encoder with bubble error correction

Abstract: This paper compares several approaches to come up with the Verilog HDL model of the thermometer-to-binary encoder with bubble error correction. It has been ...