This project implements an 8-bit Linear Feedback Shift Register (LFSR) in Verilog. An LFSR is a shift register where the input bit is a linear function (XOR) of selected previous bits (taps). It is ...

This project implements an 8-bit Linear Feedback Shift Register (LFSR) with taps at bits 6 and 5. The most significant bit (MSB) of the output represents the even parity of the lower 7 bits. The ...

LFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C and is cross-platform compatible ...