EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
EDN

Focus is on the best ASIC design flow

System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the ...
Hackaday

The Entire Process Of Building An Open Source Analog ASIC

Our hacker [Pat Deegan] of Psychogenic Technologies shows us the entire process of designing an analog ASIC. An ASIC is of ...
Design-Reuse

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
Hackaday

Opening Up ASIC Design

The odds are that if you’ve heard about application-specific integrated circuits (ASICs) at all, it’s in the context of cryptocurrency mining. For some currencies, the only way to efficiently mine ...
Semiconductor Engineering

In-Design Rail Analysis Is A Beautiful Thing

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ...
Electronic Design

Mixed-signal ASIC Design Meets Tight Deadline

Emerson, AMIS complete mixed-signal project in less than 50 weeks, half the time generally needed to complete such a project Orders were up for Emerson Process Management’s largest-selling product ...
Electronic Design

Tool Tightens Timing In ASICs' Critical Paths

Deftly optimizing ASIC critical paths, this tool rides atop existing cell-based flows to improve timing while leaving physical design largely undisturbed. Deftly optimizing ASIC critical paths, this ...
Digi Times

GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers

Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that the GLink-3D interface (GUC's Link for 3D die stacking) for the TSMC 3DFabric SoIC-X 3D stacking platform passed ...
Semiconductor Engineering

Designing 2.5D Systems

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional ...
Design-Reuse

Altera's Structured ASIC Design Flow Now ITAR-Compliant for Military Applications

SAN JOSE, Calif. -- March 12 2007--Altera Corporation (Nasdaq: ALTR) today announced that the U.S. Department of State has certified that the company's HardCopy(R) II structured ASIC design and ...