EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
IEEE

A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate

Abstract: The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of ...
GitHub

CMOS Circuit Design and SPICE Simulation using SKY130 Technology Workshop

This ten-day workshop, organized by VLSI System Design, was centered on CMOS circuit design and SPICE simulation using SKY130 technology. The sessions were structured progressively, beginning with the ...
Semiconductor Engineering

Models for Both Strained and Unstrained GAA FETs Using Neural Networks

A new technical paper titled “Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach” was published by researchers at Hanyang University ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
IEEE

Total Ionizing Dose (TID) Analysis of FinFET-Based CMOS NAND and NOR Logic Gates

Abstract: The total ionizing dose analysis of CMOS-based NAND and NOR logic gate is presented. In the normal operating conditions, universal logic gates function as expected. However, exposure to ...