Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Design-Reuse

Cache memory design in verilog IP Listing

The eSi-1650 16-bit CPU with instruction cache is targeted specifically for low-power applications, where typically an 8-bit CPU may have previously been used or where a 32-bit CPU is too big ... The ...
NextBigFuture

Analog in-memory Computing Attention Mechanism for Fast and Energy-efficient Large Language Models

A Nature paper describes an innovative analog in-memory computing (IMC) architecture tailored for the attention mechanism in ...
Semiconductor Engineering

Dynamic KV Cache Scheduling in Heterogeneous Memory Systems for LLM Inference (Rensselaer Polytechnic Institute, IBM)

A new technical paper titled “Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System” was published by researchers at Rensselaer Polytechnic Institute and IBM. “Large ...
Semiconductor Engineering

Chiplet Design Considerations

The first question design teams need to consider is what functional blocks and functions will be included in a design and how those functions will be partitioned into different chiplets. Additionally, ...

AMD patent proposes new memory module to double DDR5 speeds

The patent describes the development of high-bandwidth dual inline memory modules (HB-DIMMs) that use pseudo channels and specialized data routing to boost performance. Rather than re-engineering ...
ExtremeTech on MSN

Qualcomm Debuts Snapdragon X2 Elite and X2 Elite Extreme With up to 18 CPU Cores

Qualcomm debuted its next-generation Snapdragon X2 System on Chip (SoC) design on Wednesday, with up to 18 CPU cores, higher clock speeds, more cache, a next-generation GPU with support for higher ...