GitHub

marcinmaslanka/diode_model-verilog

🚀 Simulating a Verilog-A Diode Model in Cadence ADE This guide walks you through the steps to simulate a Verilog-A diode model in Cadence Virtuoso using ADE (Analog Design Environment). 📝 Diode ...
IEEE

Investigating Reactive Power Model for Constant Voltage Profile During Multiple Contingencies in Nairobi Load Centers Using Power World Simulation Tool

Abstract: This paper presents a proposed model for a reactive power distribution network with a constant voltage profile for Nairobi region on a daily basis case study. It began with development of ...
IEEE

Study of Constant DC-Voltage Control for VIENNA Rectifier Under No-Load Condition

Abstract: VIENNA rectifier has emerged as a promising topology for ac–dc power converter, but it has the problem of dc-link output voltage surge under no-load condition. In this article, a ...