To use LLMs and TL-Verilog to improve all existing Verilog by reducing its size, improving its maintainability, making it more configurable, and identifying bugs? How could we possibly do all that?

This repository shows how to convert a complex VHDL design into a single, synthesizable, plain-Verilog module using GHDL's synthesis feature. The example in this repository is based on the NEORV32 ...

Abstract: This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into ...

A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are ...

US reverse engineering experts ChipWorks have developed a browser that rebuilds parts of any chip into schematics and VHDL or Verilog from an analysis of the different layers of the device. ChipWorks ...

Abstract: This paper presents an implementation of the All-Digital Phase-Locked Loop circuit in Verilog HDL. It is designed using standard library cells only. NAND cells are the main bricks for all ...

The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. (March 2018: Link dead. Try the Wayback Machine.) Programmable logic devices are ...

Never in my wildest dreams did I think that the Verilog hardware description language (HDL) would spawn an industry and be a fixture of electronics design for more than 15 years. HDLs were a ...