GitHub

RISC-V-Tapeout-chip-program-week-1

Building upon the RISC-V learning journey, the focus of Week 1 . it was about the simulation and synthesis of both combinational and sequential circuit . This week was about the digital design ...
IEEE

Combinational and Sequential Design Logic for Ternary System

Abstract: In this work, an attempt has been made to design and implement combinational as well as sequential circuits by a ternary system of logic where every logic state is supported by three states, ...
GitHub

tanuka-sree628/Risc-V_SOC_-Week1-

The workshop presented a full course in RTL (Register Transfer Level) design and synthesis in Verilog HDL and free tools like Icarus Verilog, GTKWave, and Yosys. The day was organized with an equal ...
IEEE

Synthesis and verification of cyclic combinational circuits

Abstract: Prior works have demonstrated opportunities for achieving more minimized combinational circuits by introducing combinational loops during the synthesis. However, they achieved this by using ...
Design-Reuse

Latches and timing closure: a mixed bag

Digital blocks contain combinational and sequential circuits. Sequential circuits are the storage cells with outputs that reflect the past sequence of their input values, while output of the ...