IEEE

Layout Design of Low Power High Performance JK Flip-Flop with Modified Gate Diffusion Input Technique Using Cadence Virtuoso Tool for IC Design

Abstract: The proposed work focuses on the layout design of a JK flip-flop aimed at achieving lower power consumption through the innovative application of the Gate Diffusion Input (GDI) technique.
IEEE

Design and Analysis of Low Power High Speed Multi Bit Flip-Flop using Various Design Logics

Abstract: Power dissipation accounts for high-performance digital systems in the deep sub-micron region. As a result, power within compact systems is vital. A Multi-bit flip-flop(MBFF) is a sequential ...
EDN

Clocked J-K Flip-Flop

In the circuit shown above, inputs A, B, and C are all initially LOW. Output Y is supposed to go HIGH only when A, B and C goes HIGH in a certain sequence. (a) Determine the sequence that will make Y ...
GitHub

ANSH-SINGH17/SR-flipflop

**Design and Simulation of an SR Flip-Flop using CMOS Technology in LTspice This project involves the design and simulation of an SR (Set-Reset) flip-flop circuit using NMOS4 and PMOS4 transistors in ...
GitHub

JK Flip-Flop Using NAND Gates

This project is a gate-level implementation of a JK flip-flop using only NAND gates, built and simulated in Logisim Evolution (v3.7.2). The idea was to understand how the JK flip-flop works internally ...