IEEE

Layout Design of Low Power High Performance JK Flip-Flop with Modified Gate Diffusion Input Technique Using Cadence Virtuoso Tool for IC Design

Abstract: The proposed work focuses on the layout design of a JK flip-flop aimed at achieving lower power consumption through the innovative application of the Gate Diffusion Input (GDI) technique.
EDN

Clocked J-K Flip-Flop

In the circuit shown above, inputs A, B, and C are all initially LOW. Output Y is supposed to go HIGH only when A, B and C goes HIGH in a certain sequence. (a) Determine the sequence that will make Y ...
IEEE

Design of Efficient Scan Flip-Flop

Abstract: Design For Testability (DFT) is a technique used while designing the Integrated Circuit (IC) to add features to the hardware design which helps in testing the design. Scan insertion is one ...