IEEE

Non-scan design for testability for synchronous sequential circuits based on conflict analysis

Abstract: A non-scan design for testability method is presented for synchronous sequential circuits. A testability measure called conflict based on conflict analysis in the process of synchronous ...
IEEE

Power Estimation of Synchronous Sequential VLSI Circuits Using Boosting Techniques

Abstract: Power has a notable influence on the functionality and reliability of the Very Large-Scale Integration (VLSI) circuits. Thus, estimation of consumed power at an initial phase is extremely ...
Design-Reuse

Designing low-power sequential circuits using clock gating

With shrinking technologies, rapid multiplication of clock frequencies, and increasing emphasis on power reduction, low-power design is taking on a vital role. Design teams can no longer afford to ...
Massey University

Digital Electronic Systems

This course builds on the fundamentals of digital logic and the principles of computing. It provides the methodology for designing and building complex digital electronic systems. The topics are a ...
Electronic Design

Interactive Graphical Interface Enhances Micro-Programmed Sequential Machine Design (.PDF Download)

Different design approaches, techniques, and architectures are widely used for synchronous sequential machines. In particular, the micro-programmed machine approach offers important features such as ...