Design-Reuse

PCI Express Design Considerations -- RapidChip Platform ASIC vs. FPGA Design Efficiency

This paper describes the implementation differences of an IP core between FPGA and RapidChip® Platform ASIC technologies. By mapping the same complex, high-speed PCI Express core onto these two ...
Design-Reuse

HARDI Electronics teams with LSI to offer SerDes for ASIC Prototyping

LSI’s GigaBlaze SerDes Core on HapsTrak Daughter Board helps to solve difficult high speed interface issues See the new board at DAC in HARDI booth #2869 San Jose, California -- May 30, 2007--HARDI ...