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GitHub

Constructing a 2 Input XOR Gate Using Skywater 130nm CMOS Technology

This repo deals with the construction of a 2-input XOR gate using CMOS Skywater 130nm technology in xschem & obtaining its parameters through pre-layout simulation using ngspice.
GitHub

CMOS XOR Gate Design – Cadence Virtuoso

The following schematic shows the CMOS implementation of a 2-input XOR gate using complementary pull-up and pull-down networks: Figure: CMOS XOR gate schematic drawn in Cadence Virtuoso. Input A: ...
IEEE

Comparative Analysis of XOR Implementation using CMOS Logic, Domino Logic - Keeper Technique

Abstract: As technology continues to scale and advance, achieving the primary goals of design i.e., low power consumption and faster circuitry have become more feasible. The continuous advancement of ...
IEEE

Comparative performance analysis of XOR-XNOR function based high-speed CMOS full adder circuits

Abstract: This CMOS Design, Complimentary Pass Transistor Logic Design and papers presents the realization of full adder designs using Complimentary XOR-XNOR Design in a single unit. The main motive ...
Nature

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for ...