A Python-based tool called STA Combinational is intended to extract and process important data from Non-Linear Delay Model (NLDM) liberty files (.lib) and digital circuit benchmark files (.bench). It ...

Welcome to the documentation for Verilog coding of Combinational circuits! This guide will help you understand and navigate the resources available for this project. Whether you're a developer, user, ...

Abstract: In this paper we address the problem of generating large combinational circuits with good fan in and fanout distribution, high Rent factor and large number of reconvergent gates. Such ...

Verification had always been an important part of SOC design flow. As SOCs are getting more and more complex, so is their verification. Verification of a design involves simulating the all possible ...

Abstract: In this paper a simple method for fault tolerance with respect to transient or soft errors in the combinational part of sequential circuits is investigated. The memory elements of the ...