EDN

Solving FPGA I/O pin assignment challenges

Editor's Note: I've long been impressed by Xcell Journal from Xilinx, both for the quality of its production and the quality of its articles. A few weeks ago we looked at an article on Replacing ...
EDN

Binding the “Ties that Break” – Getting FPGA and PCB designers to meet at the I/O pin negotiating table

With their zero NRE and shorter design cycles, FPGA's are steadily replacing ASIC's in mid-level commercial and even higher-volume consumer applications. But as FPGA usage has steadily grown, so have ...
Hackaday

FreeSoC, For When You Need 68 I/O Pins

Like many of us, [Jon] began his journey through the magical world of microcontrollers with an Arduino. For a beginner, the Arduino is a wonderful tool, but [Jon] quickly found himself limited by the ...
IEEE

Multi-FPGA prototyping board issue: the FPGA I/O bottleneck

Abstract: Multi-FPGA boards are widely used for rapid system prototyping. As the ratio between the logic capacity and the number of I/Os for each FPGA generation is increasing, FPGA I/Os are becoming ...
Embedded

FPGA design from the outside in

FPGAs can contain millions of logic gates yet every FPGA, regardless of the complexity of its internal design, must communicate with external devices through its I/O pins. Although this statement is ...
Electronic Design

FPGA Based I/O Card Is Up For Anything

Introduced as a standalone, no-bus version of the FPGA-based Anything I/O card series, the 7I60 I/O card provides 96 I/O bits and four serial ports: two RS-232 and two RS-485. One RS-232 port is used ...