Now we have the final full adder circuit design. As nice as this design appears, it is not practical as an accumulator, e.g. a register for adding many bits at one time.

This paper contributes to a better knowledge of the behavior of conventional CMOS and CPL full-adder circuit when low voltage, less delay, low power or small power delay products are of concern.

In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p ...