EDN

From timing to power: the shift in modeling standards

There's been a shift in what's needed in modeling standards for IC design. The focus has moved from timing to power consumption. Timing modeling, which dominated much of the effort from the early to ...
IEEE

Sp2V: accelerating post-layout spice simulation using Verilog gate-level modeling

Abstract: We propose a system for accelerating post-layout simulation of digital circuits. The conventional method using standard cells for layout generation leads us to perform post-layout simulation ...
EDN

ITC: DeFacTo unveils DFT product that eliminates need for gate-level scan

DeFacTo Technologies announced at the International Test Conference a new DFT product that analyzes a register-transfer level (RTL) integrated-circuit design, creates appropriate RTL scan-test ...
Yahoo Finance

TSMC Certifies Silvaco's InVar(TM) Gate Level EM/IR Analysis Solution for 16nm FinFET Plus ...

SANTA CLARA, CA--(Marketwired - September 10, 2015) - Silvaco, Inc. today announced that TSMC has certified Silvaco's InVar electromigration (EM)/voltage drop (IR) analysis tools for 16-nanometer (nm) ...