EDN

Designers stand up for gate-level simulation

SANTA CRUZ, Calif. — In theory, static timing analysis and formal verification should render gate-level simulation unnecessary. But in reality, it's unavoidable, according to a number of engineers who ...
Semiconductor Engineering

The Case For FPGA Equivalence Checking

Formal Equivalence Checking (EC) has become a standard part of the ASIC development flow, replacing almost all gate level simulation with a rigorous consistency check between pre- and post-synthesized ...
Design-Reuse

Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification

ANDOVER, Mass.-- March 23, 2012--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its revolutionary X verification solution, ...
Design-Reuse

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...