Design-Reuse

ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

Companies Also Announce Addition of HDL Works to Actel's EDA Alliance Program CAMBERLEY, UK and EDE, Netherlands, July 26 -- Actel Corporation (Nasdaq: ACTL) and HDL Works today announced the ...
EDN

Advocates of design languages declare truce

Not long ago, the electronic design automation (EDA) industry was gearing up and taking sides on what was facetiously billed as round two in the battle of the next-generation design languages. Pundits ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
ITWire

iTWire - HDL Design House Adopts Magma's Chip Design Software

With Magma as its primary EDA vendor, HDL Design House will now be able to provide its clients with complete mixed-signal system on chip (SoC) design services, and be able to augment their current ...
EDN

Engineer creates HDL generation language

SANTA CRUZ, Calif. — A declarative, functional programming language that eases RTL code generation is now going into beta sites, and is available for free downloading from the creator's web site. The ...