EDN

HDL: A Design Flow Runs Through It

The modern hardware design flow is beginning to resemble America's great rivers. At one time they ran wild and free, but now they are constrained by an endless series of irrigation projects, dams and ...
Design-Reuse

ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

Companies Also Announce Addition of HDL Works to Actel's EDA Alliance Program CAMBERLEY, UK and EDE, Netherlands, July 26 -- Actel Corporation (Nasdaq: ACTL) and HDL Works today announced the ...
Business Wire

Mentor Graphics HDL Designer Saves Months of Design Effort with Concurrent HDL Checking

WILSONVILLE, Ore.--(BUSINESS WIRE)--Oct. 7, 2005--Mentor Graphics Corporation (Nasdaq:MENT), the leader in standards-based digital IC design creation, analysis, synthesis, and management tools, today ...
Design-Reuse

Methodology for protection and Licensing of HDL IP

HDL Intellectual Property commerce depends mainly on two factors: protection of investment and flexibility of usage. These two are diverse factors; the higher is the protection, the lower is the ...
EDN

The IP Reuse Requirements for System-Level Design Languages

As system-on-chip (SoC) design becomes more commonplace, it is apparent that problems with electronic design languages are blocking intellectual property (IP) reuse. Established hardware design ...
CU Boulder News & Events

ECEA 5361 Hardware Description Languages for FPGA Design

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...
Electronic Design

Mixed-HDL Simulator Upgraded For Speed, Space

In its latest incarnation, Model Technology's ModelSim 5.5 HDL simulator boasts significantly enhanced memory utilization, interactive debug features, testbench, and regression test support. According ...