Electronic Design

Pioneering FPGA-on-Modules: SGET Works to Develop Standard

The SGET embedded standardization body is hammering out a standard for FPGA-on-modules. Discover the benefits and how the new Harmonized FPGA Module (HFM) standard will impact the industry. Why ...
Design-Reuse

How to maximize FPGA performance

The more that can be done upfront with good coding styles, timing constraints definition, and resource planning, the easier it will be for the downstream tools to achieve timing requirements. As FPGAs ...
Design-Reuse

How to use register retiming to optimize your FPGA designs

As frequencies continue to increase in complex FPGA designs, finding the optimal point for pipeline stage insertion so as to manage routing delay issues may not be so easy. Register retiming comes in ...
Electronic Design

MathWorks speeds up FPGA-in-the-loop verification

Natick, MA. MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with the FPGA board and ...
PR Newswire

Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds

Arasan announces the immediate availability of its MIPI CSI IP supporting C-PHY v2.0 speeds of up to 54.72Gbps (when operating up to 8 Gsps with all 3 channels) for FPGA designs SAN JOSE, Calif., Nov.
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM ...

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.