Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
EDN

Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE

Editor's note: This paper is the third in a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analog component. The first ...
EDN

Verilog-AMS vs. SPICE view: An SoC verification comparison

Dozens of analog and digital IP blocks are integrated into today’s SoCs. They contain multiple voltage domains that support several modes, like Standby, Low power, Reduced Clock Mode, etc.
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
TechRepublic

Design and Verification of AMBA APB Protocol

The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on-chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low ...
mccormick.northwestern.edu

COMP_ENG 387: Real-Time Digital Systems Design and Verification with FPGAs

**Graduate students interested in taking this course for Winter 2024 should enroll in COMP_ENG 495: Real-Time Digital Systems Design and Verification with FPGAs to get graduate credit. Class ...