Running the included testbenches requires cocotb and Icarus Verilog. The testbenches can be run with pytest directly (requires cocotb-test), pytest via tox, or via cocotb makefiles.

crc_lfsr: The output remainder for generation mode The testbench directory contains a Verilog testbench for the CRC_16_serial module. Getting Started To use this module, you can clone this repository ...

If the polynomial used is a primitive, the output random state is up to 2 n - 1 state. This paper presented the designed, developed, and implemented 4, 8, 16, and 32 bit reversible LFSRs in FPGAs by ...

The really cool thing about this CPU is that it eschews the typical program counter (PC) and replaces it with a linear-feedback shift register (LFSR).