When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from ...

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design ...

In recent years, formal verification has become the verification methodology of choice for many designers and verification engineers. It's now in the mainstream marketplace, as it's easy to use, ...