The idea of this design is to implement the modified Booth algorithm to create 4 bit SFQ multiplier. In more detail, we have designed a 4-bit multiplier based on radix-4 Booth method.

Abstract: The design of a 4*4-bit multiplier using the modified Booth's algorithm in 2- mu m NMOS technology is discussed. The main features of this chip are its 62.5-MHz operating frequency and ...

One of the effective ways to speed up multiplication are by reducing the number of partial products and accelerating the accumulation. In this paper, a new architecture of hybrid Modified Booth ...