Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

A brief, but fairly technical analysis of phase noise and jitter nx minimizing them with proper phase-locked loop design. A specialized part, Silicon Labs’ Si5317 jitter-cleaning clock IC, is used as ...
IEEE

A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement

Abstract: This paper describes a Fractional-N Phase Locked Loop (PLL) for multi-phase (=M) clock generation by reducing capacitor area. The M-phase clocks from the Voltage Controlled Ring Oscillator ...
EDN

Free phase-locked loop (PLL) analysis software

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...
TechRepublic

Behavioural Modelling and Simulation of PLL Based Integer N Frequency Synthesizer using Simulink

Behavioral modeling and simulation of a PLL based integer n frequency synthesizer has been illustrated in this paper. The synthesizer generates a signal of 5.15-5.25GHz in the UNII (Unlicensed ...
Design-Reuse

True Circuits Introduces Spread Spectrum and Low Bandwidth Phase-Locked Loop Hard Macros

LOS ALTOS, California, May 5, 2003 – True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor and systems industries, today announced ...
Design-Reuse

NurLogic Implements 4.8GHz Phase Locked Loop Into AMD's Eighth-Generation Processors

SAN DIEGO – June 10, 2002 – NurLogic Design, Inc., a developer of high bandwidth connectivity solutions, today announced the successful implementation of their high-performance Phase Locked Loop ...