Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, ...
Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation ...
Cadence’s AI design flows now support TSMC’s N2 and A16 technologies, while new silicon-proven IP is available for TSMC N3P.
Synopsys has announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tape-outs. The reference flows, ...
SANTA ROSA, Calif. April 24, 2024-- Keysight Technologies, Inc. (NYSE: KEYS), Synopsys, Inc. (Nasdaq: SNPS), and Ansys (Nasdaq: ANSS) introduce a new integrated radio frequency (RF) design migration ...
Adopted by Leading Companies, the Synopsys Digital and Custom Design Flows Boost Performance and Minimize Power Consumption for Advanced SoCs on N3E and N2 MOUNTAIN VIEW, Calif., April 25, 2023 -- In ...
Siemens and TSMC deliver new certifications and design solutions for the foundry’s most advanced process technologies.
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