IEEE

Circuit design based on RAM/ROM semiconductor memory circuits

Abstract: The memory circuit is an important part of the composition of digital systems. Due to the composition of the memory structure, the memory can not only realize the function of storage but ...
TechRepublic

Logic Circuit Design Based on Series-Connected CMOS-NDR Circuit

In this paper, the authors propose a MOS-BJT-NDR circuit, which can show the Negative-Differential-Resistance (NDR) characteristic in its current-voltage curve. This NDR circuit is composed of ...
GitHub

This repository contains four laboratory assignments covering combinational circuits, sequential logic with Verilog, FPGA implementation, and memory systems.

Simplify and implement a circuit with inputs A1, A0, B1, B0 and outputs X, Y, Z using only 74LS ICs in Logisim. Learn Boolean algebra simplification and basic gate usage. Lab 2: Multiplexers, Decoders ...
Semiconductor Engineering

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National ...
EE Herald

Advanced VLSI design: Use of qubits in logic circuit design

One of the most promising nanotechnologies which can replace the present transistor based CMOS technology is the Qubit (Quantum-Dot) Cellular Automata. The major advantages of this technology are ...
Design-Reuse

VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM

VeriSilicon GSMC 0.18um Synchronous Low Power Diffusion ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/A ...
Semiconductor Engineering

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs

A new technical paper titled “Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing” was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute ...
GitHub

GatechCourses/ece2220-lab-2-quartus-ii-the-de10-and-designing-a-simple-logic-circuit-solved

Power switch is ON ( Logic 1: ON , Logic 0: OFF) Door is locked (Logic 1: Locked, Logic 0: Unlocked) Water level is high enough (Logic 1: High, Logic 0: Low) Over flow limit ( Logic 1: Above Overflow, ...