EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
EDN

Startup promises clean RTL code

San Jose, Calif. — Design automation startup Stelar Tools Inc. claims that its first product will cut 30 percent off the time it takes to move a design from initial RTL code development to synthesis.
Semiconductor Engineering

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...
Electronic Design

RTL Design Tool Brings Gains in Productivity, Quality of Results

Cadence's Joules RTL Design Studio delivers up to 5X faster register-transfer-level convergence and up to 25% improved QoR through fast, accurate, and early physical insight and guidance on improving ...
Design-Reuse

OneSpin Solutions Adds RTL-to-RTL Equivalence Checking to Product Family

MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced immediate ...