While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

SAN MATEO, Calif. — To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line ...

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool ...

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, ...

Axis Systems has developed an emulation and verification tool specifically aimed at users of intellectual property. RCC Model Compiler can link together pre-compiled blocks of RTL code. This allows ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for ...

Chip architects are faced with many decisions when designing a system on a chip (SoC). The chip often contains some number of control processors, signal processors and peripheral cores. In addition to ...

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...