IEEE

On reducing test application time for scan circuits using limited scan operations and ...

Abstract: The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test ...
IEEE

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

Abstract: It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains ...
Design-Reuse

SynTest Receives "Multiple-capture DFT system for scan-based integrated circuits" Patent ...

SAN JOSE, Calif., Oct 19, 2005-- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, was granted 33 claims on Oct. 11, 2005 under United States Patent # 6,954,887 for its ...