TechRepublic

Design of Stuck at Fault Testable Conservative Logic Based Flip-Flops and Its Application Circuits

In this paper, the authors deal with the testable design of conservative logic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the ...
EDN

Introduction to Digital Circuits – Part 3

This series of articles reviews basic concepts, and is intended for hardware and software engineers working with embedded systems. In previous sessions we covered some of the fundamental electronic ...
Ars Technica

help with Logic Circuits and specifically Flip-Flops

I'm trying to help my son understand flip-flops. He's home from Uni for holiday and has a "workbook" to get thru all about Logic Circuits and Boolean algebra etc. Between us we've been able to ...
Design-Reuse

Sequential architecture for absolutely NO hold requirement in the Shift path

Scannability has always been a challenge and with complex architectures, the challenge is exacerbated by imposing several limitations like HOLD closure, yield loss, silicon failures due to HOLD, scan ...
Design-Reuse

Dual edge sequential architecture capable of eliminating complete hold requirement from the test path

Freescale Semiconductor India Pvt. Ltd. Scannability has always been a challenge and with the complex architectures, challenges gets multifold by imposing several limitations like HOLD closure, yield ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
EDN

Shaving power/area with merged logic in SoC designs

In the modern era, there is always a requirement to achieve high frequency with lower power consumption. Achieving both targets simultaneously is very difficult and the situation becomes even more ...