GitHub

sounda2/Sequential-Logic-Design

The purpose of this project was to develop a circuit to cycle through a BCD encoding of a unique 9-digit value and display the aforementioned value on a seven-segment display (7DS). To achieve this ...
GitHub

This repository contains four laboratory assignments covering combinational circuits, sequential logic with Verilog, FPGA implementation, and memory systems.

Simplify and implement a circuit with inputs A1, A0, B1, B0 and outputs X, Y, Z using only 74LS ICs in Logisim. Learn Boolean algebra simplification and basic gate usage. Lab 2: Multiplexers, Decoders ...
mccormick.northwestern.edu

COMP_ENG 303: Advanced Digital Design

Overview of digital logic design. Implementation technologies, timing in combinational and sequential circuits, EDA tools, basic arithmetic units, introduction to simulation and synthesis using ...
IEEE

Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients

Abstract: As CMOS device sizes continue to scale down, radiation-related reliability issues are of ever-growing concern. Single event double node upsets (SEDUs) in sequential logic and single event ...
IEEE

Efficient methodology for testable reversible sequential circuit design

Abstract: Due to ultra-low power consumption, demand of reversible logic has been increased. In this article, primary intention is to not to increase the garbage output, area and delay to introduce ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...