This project implements a Finite State Machine (FSM) in Verilog to detect the specific bit pattern 01111110. The FSM outputs a high signal (y = 1) when this sequence ...

To design and simulate a sequence detector using both Moore and Mealy state machine models in Verilog HDL, and verify their functionality through a testbench using the Vivado 2023.1 simulation ...

Abstract: In this work, an analog hardware implementation of the Multi Neuronal Spike-sequence Detector (MNSD), is presented.The MNSD is a neuromorphic system for spike pattern detection based on the ...