EDN

Cadence reveals plans for SystemVerilog support

SANTA CRUZ, Calif. — Cadence Design Systems has revealed plans to support synthesizable SystemVerilog constructs in the April 2004 release of its products, and to support the “bulk” of SystemVerilog ...
EDN

SystemVerilog adoption up, Cadence survey says

SANTA CRUZ, Calif. — A recent user survey shows that adoption of the SystemVerilog language is growing rapidly, according to Cadence Design Systems. Further, the survey found, over half of ...
Business Wire

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

SAN JOSE, Calif., & WILSONVILLE, Ore.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS), and Mentor Graphics Corp. (NASDAQ:MENT) today announced that they will standardize on a verification ...
Design-Reuse

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

SAN JOSE, Calif., 25 Jan 2010-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Mitsubishi Electric Corp. has adopted Cadence® ...
CIOL

Cadence, Mentor standardize on Open SystemVerilog

It delivers on the promise of SystemVerilog with established interoperability mechanisms for verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly ...
Electronic Design

Cadence, Mentor Team To Open Up SystemVerilog Verification

When the SystemVerilog hardware description language (HDL) came onto the scene a few years ago, it promised true openness and interoperability. Here, crowed the hype, was an HDL that would enable ...
Electronic Design

Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. EDA giants ...
Electronics Weekly

Cadence makes logic verification OVM-savvy

Cadence Design Systems has added several enhancements, including support for the OVM (open-verification methodology)—to its Incisive logic-verification-tool lineup. Traditionally, verification ...
Yahoo Finance

Two More Verific Licensees Achieve Successful Exits

ALAMEDA, CA--(Marketwired - May 12, 2016) - Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers, today announced that two of its longtime customers joined a growing ...
Electronics Weekly

Cadence schedules more ‘hands-on’ design training

Cadence is running a couple more ‘hands-on’ training sessions, relating to chip and PCB design, and system interconnect design. The courses are run at the Cadence UK training centre in Bracknell. * ...
New Electronics

Cadence and Imperas support NSITEXE in development of automotive RISC V Vector processor IP

Imperas Software and Cadence Design Systems have collaborated to enable NSITEXE, part of the DENSO Corporation, to develop a RISC-V-based processor IP for functional safety and next-generation ...
Design-Reuse

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

The Open Verification Methodology Enables Simulator, Verification IP, and Language Interoperability to Deliver on Promise of SystemVerilog SAN JOSE, Calif., & WILSONVILLE, Ore. -- August 16, 2007-- ...