SystemVerilog adds several new data types, which allow hardware to be modeled at more abstract levels, using data types more intuitive to C programmers. class — an object-oriented dynamic data type, ...

Data structures called tagged unions provide type safety and brevity, making it easier to use formal verification. And a technique called pattern matching can make code both concise and expressive, he ...

The scope of the new working group is to document a SystemVerilog-compatible language extension to permit interconnect, conversion, and resolution among dissimilar net types in SystemVerilog ...

His latest, Writing Testbenches Using SystemVerilog, is aimed at getting readers with a basic understanding of VHDL, Verilog, OpenVera, or e started on using the advanced verification constructs ...