EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
EDN

Verification IP Reuse For Complex Networking Asics

Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity ...
Design-Reuse

Imperas releases new RISC-V Processor Verification IP to drive RISC-V adoption forward with a flexible methodology for all SoC adopters

Provides building blocks for RISC-V processor DV with free simulator, architectural validation test suites and SystemVerilog components for evolving Verification Ecosystem. Oxford, UK – December 9th, ...
Design-Reuse

Borrowing from software to use SystemVerilog test bench debug & analysis

Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the ...
Electronics Weekly

Parser platform lets designers innovate

To gain at least an 18 month advantage in getting a product to market, Verific Design Automation builds SystemVerilog, UPF and VHDL parser platforms which accelerates the production cycle because the ...