Design-Reuse

SystemVerilog key to new design paradigm

SAN JOSE, Calif. — The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO ...
Electronic Design

Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. EDA giants ...
Design-Reuse

Advanced Techniques for IP Design and Verification

As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...
Electronic Design

SystemVerilog Support Leads Debuggers' Upgrades

Database upgrades, clock-tree and timing debug features, and support for assertion-driven debugging have all been added to Novas' debug systems. In the latest versions of its Debussy and Verdi ...