GitHub

UART Implementation with FIFO Buffers

A simple UART (Universal Asynchronous Receiver/Transmitter) implementation in Verilog with TX/RX FIFO buffers. The testbench sends 0x55 and verifies the received data matches in the loopback test.
GitHub

Sachin-g2/verilog_uart_tx

This is a basic UART to AXI Stream IP core, written in Verilog with testbenches. The AXI4-Stream UART Transmitter (uart_tx) is designed to serialize parallel data received via an AXI4-Stream interface ...
elektormagazine

3 flavours of DMX UART/PIO/VERILOG

Shows how to create transmitters and receivers with accurate signal timing. DMX needs extra care because of frame start detection using Mark/Space/Break detection, this makes implementation ...
IEEE

FPGA based UART Design: Simulation, Synthesis & System Verilog functional verification

Abstract: The UART is a communication protocol that operates on serial data transmission (sending information bit-by-bit) between different modules asynchronously. As the number of devices increases, ...
IEEE

Design of a 9-bit UART module based on Verilog HDL

Abstract: Universal Asynchronous Receiver Transmitter (UART) is widely used in data communication process especially for its advantages of high reliability, long distance and low cost. In this paper, ...
Design-Reuse

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we ...
EDN

Using Tcl to create a virtual component in Verilog

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...