Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
elEconomista

DVCon Europe "Must See": Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

The 90-minute tutorial focuses on the use of Easier UVM and SCE-MI to help teams get started with UVM and, importantly, to future-proof their UVM verification environments by making them ...
Design-Reuse

Creating intelligent testcases using uvm_report_catcher

In this blog, we will go through the verification method for erroneous scenarios which helps you to prevent your RTL from error cases and also helps you to find out ...
Design-Reuse

Functional Verification Basics: UVM Tutorial

UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, ...
GitHub

THE UVM PRIMER CODE EXAMPLES

There is nothing worse than a syntax error in a technical teaching book; the poor student is already learning new things and the error is just an unnecessary curve ...
University of Vermont

Faculty Resources (Tutorial Services)

Faculty Resources (Tutorial Services) Curious about how our center can support your work as a faculty or staff member? This FAQ page provides comprehensive information about the services we offer, how ...