The CoValidator VHDL simulator and coverage analyzer, the first component of Impulse's forthcoming CoDeveloper hardware/software design suite, enables users to quickly identify specific lines of code ...

The simulation environment used for this task was Mentor Graphics' ADVanceMS, which is capable of simulating a complete analog and digital design, using combinations of SPICE, VHDL (with VITAL), ...

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs ...

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...

The development of VHDL was initiated in 1981 by the United States Department of Defense (DoD) to address the hardware life cycle crisis.1983-85 Development of baseline language by Intermetrics, IBM ...

Design and Simulation of 8255 Programmable Peripheral Interface Adapter Using VHDL The 8255A Programmable Peripheral Interface (PPI) implements a general-purpose I/O interface to connect ...

The simulation of the system proves all the features mention above. They have designed the system using VHDL codes in Xilinx & analog filter simulation in Matlab.

The repo contains the VHDL code and some C++ code that interfaces with the board and displays the results. If you have that particular board, it would be a good basis for a different project.

I'm an FPGA guy by day, we use VHDL exclusively at work and I've yet to find an open source alternative (gHDL etc) that holds a candle to the paid (or free but limited) tools.