GitHub

Tanushree-mm/4-bit-ADDER

Write Verilog code for a 4-bit adder. Verify functionality using a test bench. Perform synthesis and analyze: critical path, max frequency, total cells, power, and area. A full adder is a ...
IEEE

VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design

Abstract: This paper describes a VHDL modeling environment of built-in-self-test (BIST) for system on chip (SOC) testing to ease the description, verification, simulation and hardware realization. The ...
Design-Reuse

DapTechnology announces VHDL Testbench for its FireLink Extended 1394b link layer controller IP Core

Nijmegen, The Netherlands -- May 28, 2008-- DapTechnology, a world-leading supplier of advanced IEEE 1394 technology solutions to the aerospace, defense, industrial, automotive and consumer ...
TechRepublic

32 Bit Parallel Multiplier Using VHDL

In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High ...
IEEE

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

Abstract: This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) ...
Hackaday

Bit-Serial CPU: Ultra-Tiny VHDL-Based CPU With Forth Interpreter

Soft cores for FPGAs come in many different flavors, covering a wide range of applications. The Bit-Serial CPU (bcpu) soft core presented by [Richard James Howe] is interesting for taking up just ...