EDN

VHDL program enables PCI-bus-arbiter core

This Design Idea describes a VHDL implementation of a PCI 2.2-bus arbiter (Figure 1). Any PCI system may have one or more PCI-master devices. Most devices can behave as target hosts, but one must be a ...
GitHub

Embedded-Systems-VHDL-Assignments

Step 9: Initialize the visualiztion of waveform by clicking at the tick mark. You can zoom in & zoom out the waveform by clicking '+' & '-' respectively.
Electronics Weekly

A focus on VHDL

VHDL is a hardware description language for hardware engineers to define digital circuitry, targeting CPLDs (complex programmable logic device) and FPGAs (Field-programmable gate arrays). It was ...
IEEE

Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming

Abstract: A method for generation of design verification tests from behavior-level VHDL programs is presented. The method generates stimuli to execute desired control-flow paths in the given VHDL ...
IEEE

VHDL semantics and validating transformations

Abstract: Formal models are used to provide an unambiguous definition of the semantics of very high speed integrated circuit hardware description language (VHDL) and to prove equivalences of VHDL ...
GitHub

RedBlaze42/FPGA-VHDL-TrafficLights

This state machine mirrors from the french traffic lights system. There are four states which are automatically cycled by default. But there is a pedestrian button fo force the transition between CARS ...
EDN

VHDL 101 – IF, CASE, and WHEN in a Process

Last time, in the third installment of VHDL we discussed logic gates and Adders. Let’s move on to some basic VHDL structure. All HDL languages bridge what for many feels like a strange brew of ...
Hackaday

FPGA Snake Game Uses No VHDL At All

We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES ...