Although a structured way to generate names is nice, tools like Surfer can recreate the hierarchy (to some extent). In Surfer, we didn't go for the "reverse-engineer variable name"- approach (as there ...

The data objects in VHDL and Verilog form expression operands. Knowing the operand differences between the two HDLs helps you write more efficient chip-design code. Expressions consist of operators ...

I put a blog entry up on the Oasys blog about their new release, which is the first to support VHDL. But a couple of people told me it was a nice recounting of history so I decided to put a more ...

This README explains how to work with the Half Adder (HA) design using IIC-OSIC-TOOLS, including simulation in GTKWave, conversion to Verilog, and gate-level synthesis with Yosys.

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...